Formal verification

Results: 829



#Item
561L4 microkernel family / Microkernel / Thread / Kernel / Isabelle / Formal verification / Linux kernel / Memory barrier / Mach / Computer architecture / Computing / Concurrent computing

The Clustered Multikernel: An Approach to Formal Verification of Multiprocessor OS Kernels Michael von Tessin NICTA∗ and University of New South Wales Sydney, Australia

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Source URL: research.microsoft.com

Language: English - Date: 2012-04-08 02:17:07
562Model checkers / Automata theory / Digital electronics / Models of computation / Formal methods / Finite-state machine / Promela / Model checking / Formal verification / Electronic engineering / Theoretical computer science / Design

A Closed-loop Model-based Design Approach Based On Automatic Verification and Transformation Kun Zhang Jonathan Sprinkle

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Source URL: www.dsmforum.org

Language: English - Date: 2014-10-10 07:33:46
563Simulation software / Computing / Modelica / Systems engineering / Reliability engineering / Formal verification / Dymola / Functional Mock-up Interface / Object-oriented programming / Software engineering / Application software

Verification and Design Exploration through Meta Tool Integration with OpenModelica Zsolt Lattmann2, Adrian Pop1, Johan de Kleer3, Peter Fritzson1, Bill Janssen3, Sandeep Neema2, Ted Bapty2, Xenofon Koutsoukos2, Matthew

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Source URL: www.isis.vanderbilt.edu

Language: English - Date: 2014-03-27 08:06:24
564Theoretical computer science / Software development process / Mathematical proof / KeY / B-Method / Scientific modelling / Model-based testing / Formal verification / Formal methods / Science / Software development

Formal Methods in Industry: Achievements, Problems, Future Jean-Raymond Abrial Swiss Federal Institute of Technology Zurich [removed]

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Source URL: www.irisa.fr

Language: English - Date: 2006-05-20 23:41:24
565Software engineering / Design / Diagrams / Automata theory / Models of computation / Class diagram / Stereotype / Activity diagram / Sequence diagram / UML diagrams / Unified Modeling Language / Data modeling

¨ t Augsburg Universita Formal Verification of Information Flow Secure Systems with IFlow

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Source URL: www.isse.uni-augsburg.de

Language: English - Date: 2014-12-01 09:12:56
566Electronic engineering / Embedded systems / Central processing unit / Operating system / Formal verification / Embedded software / Advanced Learning and Research Institute / Ring / SIGNAL / Formal methods / Computing / Electronics

TUM TECHNISCHE UNIVERSITÄT MÜNCHEN INSTITUT FÜR INFORMATIK Seminar: Embedded Systems

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Source URL: planetic.es

Language: English - Date: 2015-01-29 04:44:26
567Formal verification / NICTA / Trustworthiness / Copyright / Trust / Computer security / Gernot Heiser / Ethics / Science / L4 microkernel family

An Architectural Approach for Cost Effective Trustworthy Systems Ihor Kuz, Liming Zhu, Len Bass, Mark Staples, Xiwei Xu NICTA Copyright 2012

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Source URL: wicsa2012.soberit.hut.fi

Language: English - Date: 2012-11-29 11:36:03
568Process calculus / Abstraction / Computing / Computer science / Logic in computer science / Formal verification / Theoretical computer science

Component-Oriented Verification of Noninterference Alessandro Aldini Marco Bernardo Dipartimento di Matematica, Informatica, Fisica e Chimica – Universit`

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Source URL: www.sti.uniurb.it

Language: English - Date: 2011-03-14 09:41:01
569Abstract interpretation / Astrée / Applied mathematics / Computer science / Formal verification / Patrick Cousot / Programming language / Abstraction / Semantics of programming languages / Formal methods / Theoretical computer science / Logic in computer science

The Verification Grand Challenge and Abstract Interpretation Patrick Cousot École normale supérieure, 45 rue d’Ulm[removed]Paris cedex 05, France Patrick.Cousot@ ens.fr

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Source URL: vstte.inf.ethz.ch

Language: English - Date: 2005-10-02 15:59:16
570Digital electronics / Diagrams / Logic in computer science / And-inverter graph / Retiming / Logic synthesis / Formal verification / Combinational logic / Standard cell / Electronic engineering / Electronic design automation / Formal methods

Verification after Synthesis Alan Mishchenko Robert Brayton Department of EECS

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Source URL: www.bvsrc.org

Language: English - Date: 2006-05-01 19:34:23
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